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LG³ëÆ®ºÏ "LM70-P6MK" DDR2 ¸Þ¸ð¸® ±¸ÀÔÇÏ°í ½Í½À´Ï´Ù.
ÀÌÇöÀÏ
2005-03-24

ÇöÀç ³ëÆ®ºÏ¿¡ ÀåÂøµÇ¾î Àִ°Ͱú ¶È°°Àº °É·Î ±¸ÀÔ ¿øÇÕ´Ï´Ù.

¾Æ·¡ ½ºÆÑÀ» °°ÀÌ º¸³» µå¸³´Ï´Ù.

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¸Þ¸ð¸® ¸ðµâ ¼Ó¼º 
¸ðµâ¸í Infineon 64T64020HDL3.7A
ÀÏ·Ã ¹øÈ£ 02076013h
Á¦Á¶ ³¯Â¥ 1 ÁÖ / 2005
¸ðµâ Å©±â 512 MB (2 rows, 4 banks)
¸ðµâ À¯Çü Unbuffered
¸Þ¸ð¸® À¯Çü DDR2 SDRAM
¸Þ¸ð¸® ¼Óµµ DDR2-533 (266 MHz)
¸ðµâÆø 64 bit
¸ðµâ Àü¾Ð SSTL 1.8
¿À·ù °ËÃâ ¹æ¹ý ¾øÀ½
°»½ÅÀ² °¨¼Ò (7.8 us), Self-Refresh
 
¸Þ¸ð¸® ŸÀ̹֠
@ 266 MHz 5.0-4-4-12  (CL-RCD-RP-RAS)
@ 266 MHz 4.0-4-4-12  (CL-RCD-RP-RAS)
@ 200 MHz 3.0-3-3-9  (CL-RCD-RP-RAS)
 
¸Þ¸ð¸® ¸ðµâ Ư¡ 
Early RAS# Precharge Áö¿øµÊ
Auto-Precharge Áö¿ø¾ÈµÊ
Precharge All Áö¿ø¾ÈµÊ
Write1/Read Burst Áö¿ø¾ÈµÊ
Buffered Address/Control Inputs Áö¿ø¾ÈµÊ
Registered Address/Control Inputs Áö¿ø¾ÈµÊ
On-Card PLL (Clock) Áö¿ø¾ÈµÊ
Buffered DQMB Inputs Áö¿ø¾ÈµÊ
Registered DQMB Inputs Áö¿ø¾ÈµÊ
Differential Clock Input Áö¿ø¾ÈµÊ
Redundant Row Address Áö¿ø¾ÈµÊ
 
¸Þ¸ð¸® ¸ðµâ Á¦Á¶ÀÚ 
ȸ»ç¸í Infineon Technologies AG
Á¦Ç° Á¤º¸ http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/prod_cat.jsp?oid=-8003

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